Non-volatile memories have been developed by the semiconductor integrated circuit industry for computer applications. Examples of non-volatile memory devices include conventional flash electronically erasable programmable read-only memories (EEPROMs). A typical non-volatile memory device is a dual gate device with a gate structure that generally includes a thin tunnel oxide layer between a source and a drain on a substrate, a polysilicon floating gate on the tunnel oxide layer, a dielectric stack on the floating gate, and a polysilicon control gate on the dielectric stack. The floating gate and the control gate, which are separated by the interpolysilicon dielectric stack, form a capacitor with a capacitance which is approximately directly proportional to the dielectric constant of the dielectric stack and approximately inversely proportional to the thickness of the dielectric stack.
During the operation of the non-volatile memory, a program or erase voltage is applied to the control gate, depending upon whether the presence of a voltage at the control gate signifies a program or erase. A voltage at the floating gate is induced by the voltage at the control gate through the capacitor formed by the dielectric stack between the floating and control gates. The ratio of the voltage induced at the floating gate to the voltage applied to the control gate is called the coupling ratio of the non-volatile memory. A conventional non-volatile memory device, for example, a NAND flash memory device, typically requires an operating voltage on the order of about 20 volts applied to the control gate to induce a sufficient voltage at the floating gate because the conventional device usually has a relatively small coupling ratio typically on the order of about 50%.
An example of a conventional interpolysilicon dielectric stack is a three-layer stack comprising a nitride layer sandwiched by two oxide layers. In general, conventional oxide and nitride materials have small dielectric constants although a nitride dielectric typically has a dielectric constant greater than that of an oxide dielectric. In a conventional non-volatile dual gate memory employing an oxide-nitride-oxide (ONO) dielectric stack as the interpolysilicon structure between the floating and control gates, the coupling ratio can be as low as 50% because of the low dielectric constants of the oxide and nitride layers. The coupling ratio of the non-volatile memory device is largely dependent upon the capacitance of the capacitor formed by the floating and control gates separated by the interpolysilicon dielectric stack. Although the capacitance and therefore the coupling ratio can be increased by decreasing the thickness of the ONO dielectric stack, the minimum thickness of the ONO dielectric stack is limited by existing processing technology. A very thin ONO dielectric stack usually has a poor data retention resulting in a low yield. A thick dielectric stack would improve the yield of the non-volatile memory devices, but it would decrease the coupling ratio, thereby necessitating a corresponding increase in the operating voltage, which is the program or erase voltage applied to the control gate. A high program or erase voltage at the control gate may be undesirable in that it may require an upconverted voltage power supply.
Therefore, there is a need for an interpolysilicon dielectric structure between the polysilicon floating and control gates with a large capacitance and therefore a large coupling ratio, to obviate the need for a high program or erase voltage to be applied to the control gate. Furthermore, there is a need for a method of fabricating a low voltage non-volatile memory device with a high yield.